1. Field of the Invention
The present invention relates to an improved layout of a semiconductor integrated circuit such as a programmable logic array (PLA), and more particularly, to an arrangement of sense amplifiers each having a pattern width greater than that of a memory cell in a memory cell array.
2. Description of the Related Art
A conventional PLA has a structure, for example, as shown in FIG. 1. In FIG. 1, numerals in0 to in2 denote input signals, 41 a control input buffer, and an AND array section (User programable AND array). The AND array section can program the presence/absence of connection between its input and output lines. Numerals SA10 to SA15 denote sense amplifiers having input terminals connected to the output lines of the AND array section. Symbol OR denotes an OR array section (User programable OR array). The OR array section can program the presence/absence of connection between its input lines (output lines of sense amplifiers SA10 to SA15) and its output lines. Numerals SA20 to SA23 denote sense amplifiers having input terminals connected to the output lines of the OR array section.
The programming devices employed in the AND array section and OR array section are, for example, erasable programmable read-only memories (EPROMs) or electrically erasable programmable read-only memories (EEPROMs).
FIG. 2 is a circuit diagram showing a circuit in which EEPROM cells 50 are used as programming devices in the AND array section. Each output line (product terms) of the AND array section is connected to a sense amplifier SAi (i=0 . . . 5) having a CMOS (complementary insulated gate type) structure.
FIG. 3 is a circuit diagram showing a circuit in which EEPROM cells 50 are used as programming devices in the OR array section. Each output line (product terms) of the OR array section is connected to a CMOS sense amplifier SA2i (i=0 . . . 3).
In FIGS. 2 and 3, the EEPROM cell 50 is constructed such that a floating gate type memory cell transistor 51 and a memory cell selection MOS transistor 52 are connected in series. One end of the memory cell transistor 51 is connected to a read line RLi or RLi'. A control gate of the memory cell transistor 51 is connected to a control gate line CG. One end of the memory cell section transistor 52 is connected to a write line WLi or WLi'. In the AND array section, a gate of each memory cell selection transistor 52 is connected to one of complementary output lines RG0, RG0 to RG2, RG2 of the control input buffer 41. In the OR array section, the gate of each memory cell selection transistor 52 is connected to one of outputs 0 to 5 of sense amplifiers SA10 to SA15.
Each of the CMOS sense amplifiers SA1i and SA2i, when they have static structures as shown in FIGS. 2 and 3, comprises seven P-channel transistors TP and four N-channel transistors TN. In addition, complementary pre-charge signals PR, PR are used as control signals.
Normally, each memory cell 50 is fabricated with a minimum design standard. By contrast, the sense amplifier SA1i (SA2i) cannot be manufactured with a minimum design standard. The reason is that the sense amplifiers SA1i and SA2i must sense a slight change in the state of the read line RLi connected to memory cell 50 and also quickly amplify and transmit the signal of the read line RLi. Furthermore, the sense amplifier SA1i (SA2i) requires 11 transistors in relation to the two transistors 51 and 52 of memory cell 50. Thus, the pattern width of the sense amplifier SA1i (SA2i) is considerably greater than that of the memory cell 50.
In the conventional PLA, however, the sense amplifiers SA1i (SA2i) connected to corresponding output lines are arranged in a line. The pattern of the PLA shown in FIG. 1 is shown in FIG. 4. As can be understood from FIG. 4, the total width of the sense amplifiers on the output side of the AND array section is greater than the total width of the AND array width and control input buffer. Similarly, the total width of the sense amplifiers on the output side of the OR array section is greater than the total width of the OR array section.
In addition, a wiring region 70 must be provided to connect the memory cells 50 and the sense amplifiers SA1i and SA2i. The wiring region 70 becomes larger, as the ratio of the total width of the sense amplifiers to that of the memory cells increases and as the number of output lines increases. The increase in wiring region 70 results in an increase in die size of the PLA integrated circuit. Further, the read lines RLi and RLi' connected to the memory cells 50 become longer. As a result, the load capacitance and resistance of read lines RLi and RLi' increase and the read-out operation speed cannot be increased.